A typical differential analog receiver in an integrated circuit contains a first stage that is powered by a first power supply, such as a VDDIO supply. The first stage is followed by a second stage that is powered by a core power supply, such as a VDD supply. VDDIO may be, for example, be 3.3 volts, 2.5 volts, 1.8 volts, or 1.5 volts. However, as integrated circuit technology scales the core power supply voltage is decreasing. For example, the VDD supply may be about 1.0 volts. Problems arise as technology scales and the voltage difference between VDDIO and VDD increases.
When power supply variations and chip IR drop in an integrated circuit are considered, a nominal VDD supply of about 1.0 volts may be as low as 0.7 volts. The output common mode of the first stage of the differential analog receiver may be higher than the input common mode of the second stage because, in one example, the output common mode of the first stage may be higher than the VDD supply voltage. In some cases, the output common mode of the first stage falls within the input common mode range of the second stage, but in other cases it may fall outside the range and, thus, the second stage will not be able to amplify the signal from the first stage.
Additionally, the differential output of the first stage may have a very large amplitude variation as a result of both the wide VDDIO range and wide input dynamic range. This can cause a reliability problem because the second stage uses native oxide devices and the maximum voltage that the gate-oxide of the second stage may withstand may be much less than the signal levels of the first stage. In some cases, the signal levels of the first stage drive a voltage of more than the maximum voltage that is allowed across the gate-oxide of the second stage, which may cause gate-oxide damage that may cause reliability problems.
A need exists for a level-shifting buffer for providing signal amplitude and/or common mode adjustment in an integrated circuit receiver.